The present invention relates to a semiconductor device and, more particularly, to a bipolar type semiconductor device suitable for use in application of high cut-off frequencies and high-speed operations.
Prior art semiconductor devices comprising a bipolar transistor construction have aimed at high-speed operations by reducing the area of the extrinsic base region, as disclosed in Japanese Patent Laid-open No. 56-142667, FIG. 1 shows a cross-section of one such semiconductor device. In this figure, a semiconductor substrate 1 comprises a collector 2 and isolation regions 3 and 3'. A region C enclosed by the isolation regions 3 and 3' is known as a silicon island which includes an emitter 9. Below the emitter 9 is a base 8. An extrinsic base region 8' surrounding the emitter 9 is electrically connected to the outside via a polycrystalline silicon film 10. This structure reduces the area of the extrinsic base region 8' while minimizing a distance D between emitter 9 and polycrystalline silicon film 10 so that the base resistance may also be lowered. In FIG. 1, reference character 7 is an N-type epitaxial layer; 20 is an insulating film; A is the distance between emitter 9 and isolation region 3; and E is the distance between intrinsic base region of base 8' and isolation region 3.
One disadvantage of the above-mentioned prior art has been the lack of consideration for the distance A between emitter 9 and isolation region 3 with respect to the time constant of the transistor construction. This has led to the failure to acquire a high and stable cut-off frequency f.sub.T.
Another disadvantage of the above prior art has been its inability to fix the position of the emitter 9 relative to the isolation region 3 due to the mask alignment error stemming from emitter formation. Because the distance A between isolation region 3 and emitter 9 is variable, it is difficult to minimize the width of the extrinsic base region 8'. This has been a significant impediment to raising the cut-off frequency.